A memory interface circuit on an integrated circuit is utilized for communicating with a memory device. Generally, data communication between an integrated circuit and a memory device may be classified as either a read memory cycle or a write memory cycle. When reading from a memory device, the memory interface circuit may capture incoming data using a data capture strobe. The data capture strobe triggers the integrated circuit to read logic states of the incoming data. Generally, the data capture strobe is asserted close to the middle of the incoming data stream (e.g., in the middle of the incoming data eye or data window) so that appropriate data is sampled.
Typically, the data capture strobe is generated according to the rising or falling edges of a clock signal. However, the data capture strobe may shift unpredictably due to variations in the process, voltage and temperature (PVT) of the integrated circuit. The shift may cause the integrated circuit to fail to accurately capture the incoming data.
Therefore, most of the memory interface circuits include a tracking circuit that monitors unwanted transitions in the data capture strobe and subsequently corrects the transitions (if any). The tracking circuit may use different phase clock signals to perform sequential sampling of the data capture strobe before determining an optimum phase shift for the clock signal. However, tracking circuits using sequential sampling are generally slow and unable to react quickly to the transitions in the data capture strobe. There are other types of tracking circuits that may be relatively quicker in sampling data compared to tracking circuits with sequential sampling. However, the implementation of such tracking circuits may be costly and may require a larger die area.
It is within this context that the embodiments described herein arise.